Coverart for item
The Resource Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, Vaibbhav Taraate, (electronic book)

Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, Vaibbhav Taraate, (electronic book)

Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog
Title
Advanced HDL Synthesis and SOC Prototyping
Title remainder
RTL Design Using Verilog
Statement of responsibility
Vaibbhav Taraate
Creator
Subject
Language
eng
Member of
Cataloging source
EBLCP
http://library.link/vocab/creatorName
Taraate, Vaibbhav
Dewey number
621.3815
Index
no index present
LC call number
TK7895.E42
Literary form
non fiction
Nature of contents
dictionaries
http://library.link/vocab/subjectName
  • Systems on a chip
  • Verilog (Computer hardware description language)
Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, Vaibbhav Taraate, (electronic book)
Instantiates
Publication
Note
  • Description based upon print version of record
  • 6.6 High-Density FPGA Fabric and Buses
Antecedent source
file reproduced from an electronic resource
Contents
  • Intro; Preface; Acknowledgements; Contents; About the Author; 1 Introduction; 1.1 Moore's Prediction and the Reality; 1.2 ASIC Designs and Shrinking Process Node; 1.3 Intel Processor Evolution; 1.4 ASIC Designs; 1.4.1 Types of ASIC; 1.5 ASIC Design Flow; 1.6 ASIC/SOC Design Challenges and Areas; 1.7 Important Takeaways and Further Discussions; References; 2 SOC Design; 2.1 SOC Designs; 2.2 SOC Design Flow; 2.2.1 Design Specifications and System Architecture; 2.2.2 RTL Design and Functional Verification; 2.2.3 Synthesis and Timing Verification; 2.2.4 Physical Design and Verification
  • 2.2.5 Prototype and Test2.3 SOC Prototyping and Challenges; 2.4 Important Takeaways and Further Discussions; 3 RTL Design Guidelines; 3.1 RTL Design Guidelines; 3.2 RTL Design Practical Scenarios; 3.2.1 Parallel Versus Priority Logic; 3.2.2 Synopsys full_case Directive; 3.2.3 Synopsys parallel_case Directive; 3.2.4 Use of casex; 3.2.5 Use of casez; 3.3 Grouping the Terms; 3.4 Tri-State Buses and Logic; 3.5 Incomplete Sensitivity List; 3.6 Sharing of Common Resources; 3.7 Design for Multiple Clock Domain; 3.8 Ordering Temporary Variables; 3.9 Gated Clocks; 3.10 Clock Enables
  • 3.11 Important Takeaways and Further Discussions4 RTL Design and Verification; 4.1 RTL Design Strategy for SOC; 4.2 RTL Verification Strategy for SOC; 4.3 Few Design Scenarios; 4.3.1 Shifting of the Data; 4.3.2 Synchronous Rising and Falling Edge Detection; 4.3.3 Priority Checking; 4.4 State Machines and Optimization; 4.4.1 Moore Machine; 4.4.2 Mealy Machine; 4.4.3 Moore Versus Mealy Machine; 4.5 RTL Design for Complex Designs; 4.6 RTL Design at Top Level; 4.7 Important Takeaways and Further Discussion; 5 Processor Cores and Architecture Design
  • 5.1 Processor Architectures and Basic Parameters5.1.1 Processor and Processor Core; 5.1.2 IO Bandwidth and Clock Rate; 5.1.3 Multitasking and Processor Clock Rate; 5.2 Processor Functionality and the Architecture Design; 5.3 Processor Architecture and Micro-architecture; 5.3.1 Processor Micro-architecture; 5.4 RTL Design and Synthesis Strategies; 5.4.1 Block-Level Design; 5.4.2 Top-Level Design; 5.5 Design Scenarios; 5.5.1 Scenario 1: Instruction Set and ALU Design; 5.5.2 Scenario 2: Data Load and Shifting; 5.5.3 Scenario 3: Parallel Data Load; 5.5.4 Scenario 4: Serial Data Processing
  • 5.5.5 Scenario 5: Program Counter5.5.6 Scenario 6: Register Files; 5.6 Performance Improvement; 5.6.1 How to Tweak the RTL to Improve the Design Performance; 5.7 Use of Processors in SOC Prototyping; 5.8 Important Takeaways and the Further Discussions; 6 Buses and Protocols in SOC Designs; 6.1 Data Transfer Schemes; 6.2 Tri-State Bus; 6.3 Serial Bus Protocols; 6.4 Bus Arbitration; 6.5 Design Scenarios; 6.5.1 Scenario 1: Static Arbitration; 6.5.2 Scenario 2: Bidirectional Data Transfer and  Registered IOs; 6.5.3 Scenario 3: UART Transmitter and Receiver Design
Dimensions
unknown
Extent
1 online resource (319 p.)
File format
one file format
Form of item
online
Isbn
9789811087769
Level of compression
unknown
Quality assurance targets
unknown
Reformatting quality
unknown
Specific material designation
remote
System control number
  • on1080075179
  • (OCoLC)1080075179
Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, Vaibbhav Taraate, (electronic book)
Publication
Note
  • Description based upon print version of record
  • 6.6 High-Density FPGA Fabric and Buses
Antecedent source
file reproduced from an electronic resource
Contents
  • Intro; Preface; Acknowledgements; Contents; About the Author; 1 Introduction; 1.1 Moore's Prediction and the Reality; 1.2 ASIC Designs and Shrinking Process Node; 1.3 Intel Processor Evolution; 1.4 ASIC Designs; 1.4.1 Types of ASIC; 1.5 ASIC Design Flow; 1.6 ASIC/SOC Design Challenges and Areas; 1.7 Important Takeaways and Further Discussions; References; 2 SOC Design; 2.1 SOC Designs; 2.2 SOC Design Flow; 2.2.1 Design Specifications and System Architecture; 2.2.2 RTL Design and Functional Verification; 2.2.3 Synthesis and Timing Verification; 2.2.4 Physical Design and Verification
  • 2.2.5 Prototype and Test2.3 SOC Prototyping and Challenges; 2.4 Important Takeaways and Further Discussions; 3 RTL Design Guidelines; 3.1 RTL Design Guidelines; 3.2 RTL Design Practical Scenarios; 3.2.1 Parallel Versus Priority Logic; 3.2.2 Synopsys full_case Directive; 3.2.3 Synopsys parallel_case Directive; 3.2.4 Use of casex; 3.2.5 Use of casez; 3.3 Grouping the Terms; 3.4 Tri-State Buses and Logic; 3.5 Incomplete Sensitivity List; 3.6 Sharing of Common Resources; 3.7 Design for Multiple Clock Domain; 3.8 Ordering Temporary Variables; 3.9 Gated Clocks; 3.10 Clock Enables
  • 3.11 Important Takeaways and Further Discussions4 RTL Design and Verification; 4.1 RTL Design Strategy for SOC; 4.2 RTL Verification Strategy for SOC; 4.3 Few Design Scenarios; 4.3.1 Shifting of the Data; 4.3.2 Synchronous Rising and Falling Edge Detection; 4.3.3 Priority Checking; 4.4 State Machines and Optimization; 4.4.1 Moore Machine; 4.4.2 Mealy Machine; 4.4.3 Moore Versus Mealy Machine; 4.5 RTL Design for Complex Designs; 4.6 RTL Design at Top Level; 4.7 Important Takeaways and Further Discussion; 5 Processor Cores and Architecture Design
  • 5.1 Processor Architectures and Basic Parameters5.1.1 Processor and Processor Core; 5.1.2 IO Bandwidth and Clock Rate; 5.1.3 Multitasking and Processor Clock Rate; 5.2 Processor Functionality and the Architecture Design; 5.3 Processor Architecture and Micro-architecture; 5.3.1 Processor Micro-architecture; 5.4 RTL Design and Synthesis Strategies; 5.4.1 Block-Level Design; 5.4.2 Top-Level Design; 5.5 Design Scenarios; 5.5.1 Scenario 1: Instruction Set and ALU Design; 5.5.2 Scenario 2: Data Load and Shifting; 5.5.3 Scenario 3: Parallel Data Load; 5.5.4 Scenario 4: Serial Data Processing
  • 5.5.5 Scenario 5: Program Counter5.5.6 Scenario 6: Register Files; 5.6 Performance Improvement; 5.6.1 How to Tweak the RTL to Improve the Design Performance; 5.7 Use of Processors in SOC Prototyping; 5.8 Important Takeaways and the Further Discussions; 6 Buses and Protocols in SOC Designs; 6.1 Data Transfer Schemes; 6.2 Tri-State Bus; 6.3 Serial Bus Protocols; 6.4 Bus Arbitration; 6.5 Design Scenarios; 6.5.1 Scenario 1: Static Arbitration; 6.5.2 Scenario 2: Bidirectional Data Transfer and  Registered IOs; 6.5.3 Scenario 3: UART Transmitter and Receiver Design
Dimensions
unknown
Extent
1 online resource (319 p.)
File format
one file format
Form of item
online
Isbn
9789811087769
Level of compression
unknown
Quality assurance targets
unknown
Reformatting quality
unknown
Specific material designation
remote
System control number
  • on1080075179
  • (OCoLC)1080075179

Library Locations

Processing Feedback ...