Coverart for item
The Resource Computer architecture : ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers, Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.), (electronic book)

Computer architecture : ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers, Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.), (electronic book)

Label
Computer architecture : ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers
Title
Computer architecture
Title remainder
ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers
Statement of responsibility
Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.)
Title variation
  • A4MMC
  • AMAS-BT
  • EAMA
  • WEED
  • WIOSCA
Creator
Contributor
Subject
Genre
Language
eng
Member of
Cataloging source
GW5XE
Dewey number
004.2/2
Index
index present
LC call number
QA76.9.A73
LC item number
A66 2010
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
Series statement
  • Lecture notes in computer science,
  • LNCS sublibrary. SL 3, Information systems and application, incl. Internet/Web and HCI
Series volume
6161
Label
Computer architecture : ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers, Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.), (electronic book)
Instantiates
Publication
Antecedent source
unknown
Bibliography note
Includes bibliographical references and author index
Color
multicolored
Contents
  • Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks
  • Trace Execution Automata in Dynamic Binary Translation
  • ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation
  • Parallelization of Particle Filter Algorithms
  • What Kinds of Applications Can Benefit from Transactional Memory?
  • Characteristics of Workloads Using the Pipeline Programming Model
  • The Search for Energy-Efficient Building Blocks for the Data Center
  • KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency
  • Guarded Power Gating in a Multi-core Setting
  • Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors
  • Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine
  • Achieving Power-Efficiency in Clusters without Distributed File System Complexity
  • What Computer Architects Need to Know about Memory Throttling
  • Predictive Power Management for Multi-core Processors
  • IOMMU: Strategies for Mitigating the IOTLB Bottleneck
  • Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality
  • Performance Characteristics of Explicit Superpage Support
  • Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm
  • Extrinsic and Intrinsic Text Cloning
  • A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms
  • Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors
  • Performance Impact of Task Mapping on the Cell BE Multicore Processor
  • Parallelization Strategy for CELL TV
  • Towards User Transparent Parallel Multimedia Computing on GPU-Clusters
  • Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture
  • On the Use of Small 2D Convolutions on GPUs
  • Can Manycores Support the Memory Requirements of Scientific Applications?
  • Parallelizing an Index Generator for Desktop Search
Control code
SPR778366753
Dimensions
unknown
Extent
1 online resource (xxvii, 378 p.)
File format
unknown
Form of item
electronic
Isbn
9783642243226
Isbn Type
(electronic bk.)
Level of compression
unknown
Quality assurance targets
not applicable
Reformatting quality
unknown
Reproduction note
Electronic resource.
Sound
unknown sound
Specific material designation
remote
Label
Computer architecture : ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised selected papers, Ana Lucia Varbanescu, Anca Molnos, Rob van Nieuwpoort (eds.), (electronic book)
Publication
Antecedent source
unknown
Bibliography note
Includes bibliographical references and author index
Color
multicolored
Contents
  • Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks
  • Trace Execution Automata in Dynamic Binary Translation
  • ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation
  • Parallelization of Particle Filter Algorithms
  • What Kinds of Applications Can Benefit from Transactional Memory?
  • Characteristics of Workloads Using the Pipeline Programming Model
  • The Search for Energy-Efficient Building Blocks for the Data Center
  • KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency
  • Guarded Power Gating in a Multi-core Setting
  • Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors
  • Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine
  • Achieving Power-Efficiency in Clusters without Distributed File System Complexity
  • What Computer Architects Need to Know about Memory Throttling
  • Predictive Power Management for Multi-core Processors
  • IOMMU: Strategies for Mitigating the IOTLB Bottleneck
  • Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality
  • Performance Characteristics of Explicit Superpage Support
  • Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm
  • Extrinsic and Intrinsic Text Cloning
  • A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms
  • Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors
  • Performance Impact of Task Mapping on the Cell BE Multicore Processor
  • Parallelization Strategy for CELL TV
  • Towards User Transparent Parallel Multimedia Computing on GPU-Clusters
  • Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture
  • On the Use of Small 2D Convolutions on GPUs
  • Can Manycores Support the Memory Requirements of Scientific Applications?
  • Parallelizing an Index Generator for Desktop Search
Control code
SPR778366753
Dimensions
unknown
Extent
1 online resource (xxvii, 378 p.)
File format
unknown
Form of item
electronic
Isbn
9783642243226
Isbn Type
(electronic bk.)
Level of compression
unknown
Quality assurance targets
not applicable
Reformatting quality
unknown
Reproduction note
Electronic resource.
Sound
unknown sound
Specific material designation
remote

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