Coverart for item
The Resource Customizable computing, Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao, (electronic book)

Customizable computing, Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao, (electronic book)

Label
Customizable computing
Title
Customizable computing
Statement of responsibility
Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao
Creator
Contributor
Author
Subject
Language
eng
Summary
Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems
Member of
Cataloging source
CaBNVSL
http://library.link/vocab/creatorName
Chen, Yu-Ting
Dewey number
004.22
Illustrations
illustrations
Index
no index present
LC call number
QA76.9.A73
LC item number
C443 2015
Literary form
non fiction
Nature of contents
  • dictionaries
  • abstracts summaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorDate
fl.2015
http://library.link/vocab/relatedWorkOrContributorName
  • Cong, Jason.
  • Gill, Michael.
  • Reinman, Glenn.
  • Xiao, Bingjun.
http://library.link/vocab/subjectName
Computer architecture
Target audience
  • adult
  • specialized
Label
Customizable computing, Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao, (electronic book)
Instantiates
Publication
Bibliography note
Includes bibliographical references (pages 89-103)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. Introduction --
  • 2. Road map -- 2.1 Customizable system-on-chip design -- 2.1.1 Compute resources -- 2.1.2 On-chip memory hierarchy -- 2.1.3 Network-on-chip -- 2.2 Software layer --
  • 3. Customization of cores -- 3.1 Introduction -- 3.2 Dynamic core scaling and defeaturing -- 3.3 Core fusion -- 3.4 Customized instruction set extensions -- 3.4.1 Vector instructions -- 3.4.2 Custom compute engines -- 3.4.3 Reconfigurable instruction sets -- 3.4.4 Compiler support for custom instructions --
  • 4. Loosely coupled compute engines -- 4.1 Introduction -- 4.2 Loosely coupled accelerators -- 4.2.1 Wire-speed processor -- 4.2.2 Comparing hardware and software LCA management -- 4.2.3 Utilizing LCAs -- 4.3 Accelerators using field programmable gate arrays -- 4.4 Coarse-grain reconfigurable arrays -- 4.4.1 Static mapping -- 4.4.2 Run-time mapping -- 4.4.3 CHARM -- 4.4.4 Using composable accelerators --
  • 5. On-chip memory customization -- 5.1 Introduction -- 5.1.1 Caches and buffers (scratchpads) -- 5.1.2 On-chip memory system customizations -- 5.2 CPU cache customizations -- 5.2.1 Coarse-grain customization strategies -- 5.2.2 Fine-grain customization strategies -- 5.3 Buffers for accelerator-rich architectures -- 5.3.1 Shared buffer system design for accelerators -- 5.3.2 Customization of buffers inside an accelerator -- 5.4 Providing buffers in caches for CPUs and accelerators -- 5.4.1 Providing software-managed scratchpads for CPUs -- 5.4.2 Providing buffers for accelerators -- 5.5 Caches with disparate memory technologies -- 5.5.1 Coarse-grain customization strategies -- 5.5.2 Fine-grain customization strategies --
  • 6. Interconnect customization -- 6.1 Introduction -- 6.2 Topology customization -- 6.2.1 Application-specific topology synthesis -- 6.2.2 Reconfigurable shortcut insertion -- 6.2.3 Partial crossbar synthesis and reconfiguration -- 6.3 Routing customization -- 6.3.1 Application-aware deadlock-free routing -- 6.3.2 Data flow synthesis -- 6.4 Customization enabled by new device/circuit technologies -- 6.4.1 Optical interconnects -- 6.4.2 Radio-frequency interconnects -- 6.4.3 RRAM-based interconnects --
  • 7. Concluding remarks -- Bibliography -- Authors' biographies
Control code
201505CAC033
Dimensions
unknown
Extent
1 PDF (xi, 106 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627057677
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00650ED1V01Y201505CAC033
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader
Label
Customizable computing, Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao, (electronic book)
Publication
Bibliography note
Includes bibliographical references (pages 89-103)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. Introduction --
  • 2. Road map -- 2.1 Customizable system-on-chip design -- 2.1.1 Compute resources -- 2.1.2 On-chip memory hierarchy -- 2.1.3 Network-on-chip -- 2.2 Software layer --
  • 3. Customization of cores -- 3.1 Introduction -- 3.2 Dynamic core scaling and defeaturing -- 3.3 Core fusion -- 3.4 Customized instruction set extensions -- 3.4.1 Vector instructions -- 3.4.2 Custom compute engines -- 3.4.3 Reconfigurable instruction sets -- 3.4.4 Compiler support for custom instructions --
  • 4. Loosely coupled compute engines -- 4.1 Introduction -- 4.2 Loosely coupled accelerators -- 4.2.1 Wire-speed processor -- 4.2.2 Comparing hardware and software LCA management -- 4.2.3 Utilizing LCAs -- 4.3 Accelerators using field programmable gate arrays -- 4.4 Coarse-grain reconfigurable arrays -- 4.4.1 Static mapping -- 4.4.2 Run-time mapping -- 4.4.3 CHARM -- 4.4.4 Using composable accelerators --
  • 5. On-chip memory customization -- 5.1 Introduction -- 5.1.1 Caches and buffers (scratchpads) -- 5.1.2 On-chip memory system customizations -- 5.2 CPU cache customizations -- 5.2.1 Coarse-grain customization strategies -- 5.2.2 Fine-grain customization strategies -- 5.3 Buffers for accelerator-rich architectures -- 5.3.1 Shared buffer system design for accelerators -- 5.3.2 Customization of buffers inside an accelerator -- 5.4 Providing buffers in caches for CPUs and accelerators -- 5.4.1 Providing software-managed scratchpads for CPUs -- 5.4.2 Providing buffers for accelerators -- 5.5 Caches with disparate memory technologies -- 5.5.1 Coarse-grain customization strategies -- 5.5.2 Fine-grain customization strategies --
  • 6. Interconnect customization -- 6.1 Introduction -- 6.2 Topology customization -- 6.2.1 Application-specific topology synthesis -- 6.2.2 Reconfigurable shortcut insertion -- 6.2.3 Partial crossbar synthesis and reconfiguration -- 6.3 Routing customization -- 6.3.1 Application-aware deadlock-free routing -- 6.3.2 Data flow synthesis -- 6.4 Customization enabled by new device/circuit technologies -- 6.4.1 Optical interconnects -- 6.4.2 Radio-frequency interconnects -- 6.4.3 RRAM-based interconnects --
  • 7. Concluding remarks -- Bibliography -- Authors' biographies
Control code
201505CAC033
Dimensions
unknown
Extent
1 PDF (xi, 106 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627057677
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00650ED1V01Y201505CAC033
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader

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