Coverart for item
The Resource Design and test technology for dependable systems-on-chip, Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors

Design and test technology for dependable systems-on-chip, Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors

Label
Design and test technology for dependable systems-on-chip
Title
Design and test technology for dependable systems-on-chip
Statement of responsibility
Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors
Contributor
Subject
Language
eng
Summary
"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--
Member of
Assigning source
Provided by publisher
Cataloging source
N$T
Dewey number
621.3815
Illustrations
illustrations
Index
index present
LC call number
TK7895.E42
LC item number
D47 2010eb
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorDate
  • 1941-
  • 1972-
  • 1951-
http://library.link/vocab/relatedWorkOrContributorName
  • Ubar, Raimund
  • Raik, Jaan
  • Vierhaus, Heinrich Theodor
http://library.link/vocab/subjectName
  • Systems on a chip
  • Networks on a chip
  • Systems on a chip
  • Networks on a chip
Label
Design and test technology for dependable systems-on-chip, Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors
Instantiates
Publication
Antecedent source
unknown
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Section 1. Design, modeling, and verification -- section 2. Faults, compensation and repair -- section 3. Fault simulation and fault injection -- section 4. Test technology for systems-on-chip -- section 5. Test planning, compression and compaction in SoC's
Control code
KNOVEL713272704
Dimensions
unknown
Extent
1 online resource (xxvi, 550 pages)
File format
unknown
Form of item
online
Isbn
9781621989547
Level of compression
unknown
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations
Quality assurance targets
not applicable
Reformatting quality
unknown
Sound
unknown sound
Specific material designation
remote
Label
Design and test technology for dependable systems-on-chip, Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors
Publication
Antecedent source
unknown
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Section 1. Design, modeling, and verification -- section 2. Faults, compensation and repair -- section 3. Fault simulation and fault injection -- section 4. Test technology for systems-on-chip -- section 5. Test planning, compression and compaction in SoC's
Control code
KNOVEL713272704
Dimensions
unknown
Extent
1 online resource (xxvi, 550 pages)
File format
unknown
Form of item
online
Isbn
9781621989547
Level of compression
unknown
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations
Quality assurance targets
not applicable
Reformatting quality
unknown
Sound
unknown sound
Specific material designation
remote

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