Coverart for item
The Resource Die-stacking architecture, Yuan Xie, Jishen Zhao, (electronic book)

Die-stacking architecture, Yuan Xie, Jishen Zhao, (electronic book)

Label
Die-stacking architecture
Title
Die-stacking architecture
Statement of responsibility
Yuan Xie, Jishen Zhao
Creator
Contributor
Author
Subject
Language
eng
Summary
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology
Member of
Cataloging source
CaBNVSL
http://library.link/vocab/creatorDate
1973-
http://library.link/vocab/creatorName
Xie, Yuan
Dewey number
621.3815
Illustrations
illustrations
Index
no index present
LC call number
TK7874.893
LC item number
.X543 2015
Literary form
non fiction
Nature of contents
  • dictionaries
  • abstracts summaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Zhao, Jishen.
http://library.link/vocab/subjectName
  • Three-dimensional integrated circuits
  • Computer architecture
Target audience
  • adult
  • specialized
Label
Die-stacking architecture, Yuan Xie, Jishen Zhao, (electronic book)
Instantiates
Publication
Bibliography note
Includes bibliographical references (pages 99-111)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. 3D integration technology -- 1.1 3D integrated circuits vs. 3D packaging -- 1.2 Different process technologies for 3D ICs -- 1.3 The impact of 3D technology on 3D microprocessor partitioning --
  • 2. Benefits of 3D integration -- 2.1 Wire length reduction -- 2.2 Memory bandwidth improvement -- 2.3 Heterogenous integration -- 2.4 Cost-effective architecture --
  • 3. Fine-granularity 3D processor design -- 3.1 3D cache partitioning -- 3.1.1 3D cache partitioning strategies -- 3.1.2 Design exploration using 3DCacti -- 3.2 3D Partitioning for logic blocks --
  • 4. Coarse-granularity 3D processor design -- 4.1 3D Caches stacking -- 4.2 3D Main memory stacking -- 4.3 3D On-chip stacked memory: cache or main memory? -- 4.3.1 On-chip main memory -- 4.3.2 3D-stacked LLC -- 4.3.3 Dynamic approach -- 4.4 PicoServer --
  • 5. 3D GPU architecture -- 5.1 3D-stacked GPU memory -- 5.2 3D-stacked GPU processor --
  • 6. 3D network-on-chip -- 6.1 3D NoC router design -- 6.2 3D NoC topology design -- 6.3 3D optical NoC design -- 6.4 Impact of 3D technology on NoC designs --
  • 7. Thermal analysis and thermal-aware design -- 7.1 Thermal analysis -- 7.2 Thermal-aware floorplanning for 3D processors -- 7.3 Thermal-herding: thermal-aware architecture design --
  • 8. Cost analysis for 3D ICs -- 8.1 3D cost model -- 8.2 Cost evaluation for many-core microprocessor designs -- 8.2.1 Cost evaluation with homogeneous partitioning -- 8.2.2 Cost evaluation with heterogeneous partitioning --
  • 9. Conclusion -- Bibliography -- Authors' biographies
Control code
201505CAC031
Dimensions
unknown
Extent
1 PDF (xiii, 113 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627057653
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00644ED1V01Y201505CAC031
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader
Label
Die-stacking architecture, Yuan Xie, Jishen Zhao, (electronic book)
Publication
Bibliography note
Includes bibliographical references (pages 99-111)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. 3D integration technology -- 1.1 3D integrated circuits vs. 3D packaging -- 1.2 Different process technologies for 3D ICs -- 1.3 The impact of 3D technology on 3D microprocessor partitioning --
  • 2. Benefits of 3D integration -- 2.1 Wire length reduction -- 2.2 Memory bandwidth improvement -- 2.3 Heterogenous integration -- 2.4 Cost-effective architecture --
  • 3. Fine-granularity 3D processor design -- 3.1 3D cache partitioning -- 3.1.1 3D cache partitioning strategies -- 3.1.2 Design exploration using 3DCacti -- 3.2 3D Partitioning for logic blocks --
  • 4. Coarse-granularity 3D processor design -- 4.1 3D Caches stacking -- 4.2 3D Main memory stacking -- 4.3 3D On-chip stacked memory: cache or main memory? -- 4.3.1 On-chip main memory -- 4.3.2 3D-stacked LLC -- 4.3.3 Dynamic approach -- 4.4 PicoServer --
  • 5. 3D GPU architecture -- 5.1 3D-stacked GPU memory -- 5.2 3D-stacked GPU processor --
  • 6. 3D network-on-chip -- 6.1 3D NoC router design -- 6.2 3D NoC topology design -- 6.3 3D optical NoC design -- 6.4 Impact of 3D technology on NoC designs --
  • 7. Thermal analysis and thermal-aware design -- 7.1 Thermal analysis -- 7.2 Thermal-aware floorplanning for 3D processors -- 7.3 Thermal-herding: thermal-aware architecture design --
  • 8. Cost analysis for 3D ICs -- 8.1 3D cost model -- 8.2 Cost evaluation for many-core microprocessor designs -- 8.2.1 Cost evaluation with homogeneous partitioning -- 8.2.2 Cost evaluation with heterogeneous partitioning --
  • 9. Conclusion -- Bibliography -- Authors' biographies
Control code
201505CAC031
Dimensions
unknown
Extent
1 PDF (xiii, 113 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627057653
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00644ED1V01Y201505CAC031
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader

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