Coverart for item
The Resource High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer, (electronic book)

High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer, (electronic book)

Label
High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings
Title
High Performance Embedded Architectures and Compilers
Title remainder
Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings
Statement of responsibility
edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer
Creator
Contributor
Subject
Language
eng
Summary
This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications
Member of
Cataloging source
MND
http://library.link/vocab/creatorName
Hutchison, David
Dewey number
004
Image bit depth
0
Index
no index present
LC call number
QA76.9.C62
Literary form
non fiction
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
  • Sudan, Madhu
  • Steffen, Bernhard
  • Mattern, Friedemann
  • Mitchell, John C
  • Martonosi, Margaret
  • Kleinberg, Jon M
  • Kittler, Josef
  • Naor, Moni
  • Nierstrasz, Oscar
  • Tygar, Doug
  • Pandu Rangan, C
  • Weikum, Gerhard
  • Kanade, Takeo
  • Emer, Joel
  • Terzopoulos, Demetri
  • Ungerer, Theo
  • Seznec, André
  • Vardi, Moshe Y
  • O'Boyle, M.
Series statement
Lecture notes in computer science,
Series volume
5409
http://library.link/vocab/subjectName
  • Computer Communication Networks
  • Data transmission systems
  • Logic design
  • Computer science
  • Programming Languages, Compilers, Interpreters
  • Logic Design
  • Processor Architectures
  • Input/Output and Data Communications
  • Computer Science
  • Arithmetic and Logic Structures
Label
High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer, (electronic book)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor
Control code
SPR311305866
Dimensions
unknown
Extent
1 online resource (:
File format
multiple file formats
Form of item
online
Isbn
9783540929901
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/978-3-540-92990-1
Other physical details
v.: digital.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
Label
High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer, (electronic book)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Invited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor
Control code
SPR311305866
Dimensions
unknown
Extent
1 online resource (:
File format
multiple file formats
Form of item
online
Isbn
9783540929901
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/978-3-540-92990-1
Other physical details
v.: digital.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote

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