Coverart for item
The Resource International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems : [January, 2002, Hawaii], edited by Alex Veidenbaum, Kazuki Joe ; [supported by DARPA/ITO PAC/C Program]

International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems : [January, 2002, Hawaii], edited by Alex Veidenbaum, Kazuki Joe ; [supported by DARPA/ITO PAC/C Program]

Label
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems : [January, 2002, Hawaii]
Title
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Title remainder
[January, 2002, Hawaii]
Statement of responsibility
edited by Alex Veidenbaum, Kazuki Joe ; [supported by DARPA/ITO PAC/C Program]
Title variation
  • Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
  • Innovative Architecture for Future Generation High-Performance Processors and Systems
  • IWIA'02
  • International Workshop on Innovative Architectures
  • Workshop on Innovative Architectures
  • IWIA
Creator
Contributor
Subject
Genre
Language
eng
Related
Member of
Cataloging source
OCLCE
Index
index present
LC call number
QA76.9.A73
LC item number
I53 2002
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2002
http://bibfra.me/vocab/lite/meetingName
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
  • Veidenbaum, Alex
  • Joe, Kazuki
  • DARPA/ITO PAC/C Program
http://library.link/vocab/subjectName
  • Computer architecture
  • High performance computing
  • High performance processors
Label
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems : [January, 2002, Hawaii], edited by Alex Veidenbaum, Kazuki Joe ; [supported by DARPA/ITO PAC/C Program]
Instantiates
Publication
Note
  • Cover title
  • "This edited volume contains a collection of papers that originated from presentations at the 2002 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02) which was held on the Big Island of Hawai'i in January of 2002. -- Preface
  • "IEEE Computer Society Order Number PR01635"--Title page verso
Antecedent source
file reproduced from original
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • Trading Bandwidth for Latency: Managing Continuations Through a Carpet Bag Cache
  • R.C. Murphy and P.M. Kogge
  • Architecture and Compiler Co-Optimization for High Performance Computing
  • H. Nakamura, M. Kondo, T. Ohneda, M. Fujita, S. Chiba, M. Sato and T. Boku
  • Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor
  • T. Kodaka, K. Kimura and H. Kasahara
  • Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures
  • P.M.W. Knijnenburg, A. Ramirez, F. Latorre, J. Larriba and M. Valero
  • Preliminary Evaluation of a Binary Translation System for Multithreaded Processors
  • K. Ootsu, T. Yokota, T. Ono and T. Baba
  • Power and Performance Fitting in Nanometer Design
  • A Low Latency High Bandwidth Network Interface Prototype for PC Cluster
  • N. Tanabe, Y. Hamada, H. Nakajo, H. Imashiro, J. Yamamoto, T. Kudoh and H. Amano
  • Design and Implementation of Interrupt Packaging Mechanisms
  • K. Nakashima, S. Kusakabe, H. Taniguchi and M. Amamiya
  • A Networking Oriented Data-Driven Processor: CUE
  • H. Nishikawa and R. Kurebayashi
  • T. Sato, T. Koushiro, A. Chiyonobu and I. Arita
  • Reducing Power with an L0 Instruction Cache Using History-Based Prediction
  • W. Tang, A.V. Veidenbaum and A. Nicolau
  • Tight Non-linear Loop Timing Estimation
  • R.A. van Engelen and K.A. Gallivan
  • Exploring Advanced Architectures Using Performance Prediction
  • D.J. Kerbyson, H.J. Wasserman and A. Hoisie
Control code
IEEE762654300
Dimensions
unknown
Extent
1 online resource (viii, 113 pages)
File format
one file format
Form of item
online
Media category
computer
Media MARC source
rdamedia
Media type code
c
Specific material designation
remote
System control number
  • ocn762654300
  • (OCoLC)762654300
Label
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems : [January, 2002, Hawaii], edited by Alex Veidenbaum, Kazuki Joe ; [supported by DARPA/ITO PAC/C Program]
Publication
Note
  • Cover title
  • "This edited volume contains a collection of papers that originated from presentations at the 2002 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02) which was held on the Big Island of Hawai'i in January of 2002. -- Preface
  • "IEEE Computer Society Order Number PR01635"--Title page verso
Antecedent source
file reproduced from original
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • Trading Bandwidth for Latency: Managing Continuations Through a Carpet Bag Cache
  • R.C. Murphy and P.M. Kogge
  • Architecture and Compiler Co-Optimization for High Performance Computing
  • H. Nakamura, M. Kondo, T. Ohneda, M. Fujita, S. Chiba, M. Sato and T. Boku
  • Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor
  • T. Kodaka, K. Kimura and H. Kasahara
  • Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures
  • P.M.W. Knijnenburg, A. Ramirez, F. Latorre, J. Larriba and M. Valero
  • Preliminary Evaluation of a Binary Translation System for Multithreaded Processors
  • K. Ootsu, T. Yokota, T. Ono and T. Baba
  • Power and Performance Fitting in Nanometer Design
  • A Low Latency High Bandwidth Network Interface Prototype for PC Cluster
  • N. Tanabe, Y. Hamada, H. Nakajo, H. Imashiro, J. Yamamoto, T. Kudoh and H. Amano
  • Design and Implementation of Interrupt Packaging Mechanisms
  • K. Nakashima, S. Kusakabe, H. Taniguchi and M. Amamiya
  • A Networking Oriented Data-Driven Processor: CUE
  • H. Nishikawa and R. Kurebayashi
  • T. Sato, T. Koushiro, A. Chiyonobu and I. Arita
  • Reducing Power with an L0 Instruction Cache Using History-Based Prediction
  • W. Tang, A.V. Veidenbaum and A. Nicolau
  • Tight Non-linear Loop Timing Estimation
  • R.A. van Engelen and K.A. Gallivan
  • Exploring Advanced Architectures Using Performance Prediction
  • D.J. Kerbyson, H.J. Wasserman and A. Hoisie
Control code
IEEE762654300
Dimensions
unknown
Extent
1 online resource (viii, 113 pages)
File format
one file format
Form of item
online
Media category
computer
Media MARC source
rdamedia
Media type code
c
Specific material designation
remote
System control number
  • ocn762654300
  • (OCoLC)762654300

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