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The Resource Research infrastructures for hardware accelerators, Yakun Sophia Shao and David Brooks

Research infrastructures for hardware accelerators, Yakun Sophia Shao and David Brooks

Label
Research infrastructures for hardware accelerators
Title
Research infrastructures for hardware accelerators
Statement of responsibility
Yakun Sophia Shao and David Brooks
Creator
Contributor
Author
Subject
Language
eng
Summary
Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas
Member of
Cataloging source
CaBNVSL
http://library.link/vocab/creatorName
Shao, Yakun Sophia
Dewey number
621.3916
Illustrations
illustrations
Index
no index present
LC call number
TK7895.M5
LC item number
S427 2016
Literary form
non fiction
Nature of contents
  • dictionaries
  • abstracts summaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Brooks, David.
http://library.link/vocab/subjectName
  • Microprocessors
  • High performance computing
Target audience
  • adult
  • specialized
Label
Research infrastructures for hardware accelerators, Yakun Sophia Shao and David Brooks
Instantiates
Publication
Bibliography note
Includes bibliographical references (pages 73-83)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. Why accelerators, now? -- 1.1 What is an accelerator? -- 1.2 A tale of two scalings -- 1.2.1 Moore scaling -- 1.2.2 Dennard scaling -- 1.3 The combination of Moore and Dennard scaling -- 1.3.1 Moore + Dennard, where we were -- 1.3.2 Moore scaling only, where we are -- 1.3.3 Dennard only, where we are unlikely to be -- 1.3.4 A future without scaling: "The winter of despair" -- 1.4 To live without scaling: "A spring of hope" -- 1.4.1 Why not architectural scaling? -- 1.4.2 Specialization makes a difference -- 1.4.3 A call for tools in the era of accelerators --
  • 2. A taxonomy of accelerators -- 2.1 Not all apples are alike -- 2.2 Accelerator taxonomy -- 2.2.1 Accelerators that are part of the pipeline -- 2.2.2 Accelerators that are attached to cache -- 2.2.3 Accelerators that are attached to the memory bus -- 2.2.4 Accelerators that are attached to the I/O bus --
  • 3. Accelerator design flow 101 -- 3.1 Standard RTL design flow -- 3.2 High-level synthesis -- 3.2.1 Bluespec SystemVerilog -- 3.2.2 Genesis2 -- 3.2.3 Xilinx Vivado -- 3.2.4 Delite -- 3.2.5 Lime -- 3.2.6 ChiseL -- 3.2.7 Spiral -- 3.2.8 PyMTL --
  • 4. Accelerator modeling -- 4.1 Limitations of the RTL-based design flow -- 4.2 Pre-RTL modeling, Aladdin -- 4.2.1 Optimization phase -- 4.2.2 Realization phase -- 4.2.3 Integration with memory system -- 4.2.4 Limitations -- 4.2.5 Aladdin validation -- 4.2.6 Algorithm-to-solution time -- 4.2.7 Case study: Gemm design space --
  • 5. Workload characterization for accelerators -- 5.1 ISA-independent workload characterization, WIICA -- 5.1.1 Why ISA-independent? -- 5.1.2 Methodology and background -- 5.1.3 Compute -- 5.1.4 Memory -- 5.1.5 Control -- 5.1.6 Putting it all together --
  • 6. Accelerator benchmarks --
  • 7. Future directions -- Bibliography -- Authors' biographies
Control code
201511CAC034
Dimensions
unknown
Extent
1 PDF (xiii, 85 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627058315
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00677ED1V01Y201511CAC034
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader
Label
Research infrastructures for hardware accelerators, Yakun Sophia Shao and David Brooks
Publication
Bibliography note
Includes bibliographical references (pages 73-83)
Carrier category
online resource
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type MARC source
rdacontent
Contents
  • 1. Why accelerators, now? -- 1.1 What is an accelerator? -- 1.2 A tale of two scalings -- 1.2.1 Moore scaling -- 1.2.2 Dennard scaling -- 1.3 The combination of Moore and Dennard scaling -- 1.3.1 Moore + Dennard, where we were -- 1.3.2 Moore scaling only, where we are -- 1.3.3 Dennard only, where we are unlikely to be -- 1.3.4 A future without scaling: "The winter of despair" -- 1.4 To live without scaling: "A spring of hope" -- 1.4.1 Why not architectural scaling? -- 1.4.2 Specialization makes a difference -- 1.4.3 A call for tools in the era of accelerators --
  • 2. A taxonomy of accelerators -- 2.1 Not all apples are alike -- 2.2 Accelerator taxonomy -- 2.2.1 Accelerators that are part of the pipeline -- 2.2.2 Accelerators that are attached to cache -- 2.2.3 Accelerators that are attached to the memory bus -- 2.2.4 Accelerators that are attached to the I/O bus --
  • 3. Accelerator design flow 101 -- 3.1 Standard RTL design flow -- 3.2 High-level synthesis -- 3.2.1 Bluespec SystemVerilog -- 3.2.2 Genesis2 -- 3.2.3 Xilinx Vivado -- 3.2.4 Delite -- 3.2.5 Lime -- 3.2.6 ChiseL -- 3.2.7 Spiral -- 3.2.8 PyMTL --
  • 4. Accelerator modeling -- 4.1 Limitations of the RTL-based design flow -- 4.2 Pre-RTL modeling, Aladdin -- 4.2.1 Optimization phase -- 4.2.2 Realization phase -- 4.2.3 Integration with memory system -- 4.2.4 Limitations -- 4.2.5 Aladdin validation -- 4.2.6 Algorithm-to-solution time -- 4.2.7 Case study: Gemm design space --
  • 5. Workload characterization for accelerators -- 5.1 ISA-independent workload characterization, WIICA -- 5.1.1 Why ISA-independent? -- 5.1.2 Methodology and background -- 5.1.3 Compute -- 5.1.4 Memory -- 5.1.5 Control -- 5.1.6 Putting it all together --
  • 6. Accelerator benchmarks --
  • 7. Future directions -- Bibliography -- Authors' biographies
Control code
201511CAC034
Dimensions
unknown
Extent
1 PDF (xiii, 85 pages)
File format
multiple file formats
Form of item
online
Isbn
9781627058315
Media category
electronic
Media MARC source
isbdmedia
Other control number
10.2200/S00677ED1V01Y201511CAC034
Other physical details
illustrations.
Reformatting quality
access
Specific material designation
remote
System details
System requirements: Adobe Acrobat Reader

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