Design for AT-Speed Test, Diagnosis and Measurement

Resource Information

The work Design for AT-Speed Test, Diagnosis and Measurement represents a distinct intellectual or artistic creation found in Sydney Jones Library, University of Liverpool. This resource is a combination of several types including: Work, Language Material, Books.

Label

Design for AT-Speed Test, Diagnosis and Measurement

Statement of responsibility

by Benoit Nadeau-Dostie

Creator

• Nadeau-Dostie, Benoit

Language

eng

Summary

This reference offers practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design aims to help solve problems before any DFT is attempted

Cataloging source

UkLiU

LC call number

TK7874

Nature of contents

dictionaries